1. Field of the Invention
The present invention relates to variable operation speed transistors, and more particularly to a MOS transistor for which the operation speed is different depending on the input signals, thereby making it possible to turn on the MOS transistor at a high speed, and to turn off the MOS transistor at a low speed, or vice versa.
2. Description of Prior Art
FIGS. 1 and 2 illustrate the layout of conventional MOSFET 100.
Referring to FIG. 1, there is illustrated the layout of a MOS transistor in which the width of gate 110 is increased to increase the current capacity. Further, for this transistor, source 130 and drain 140 are formed at opposite sides of gate 110. The source or drain regions may be referenced with different names depending on the type of the substrate and the direction of the current, and thus are herein referred to as "source/drain" regions. Input signal A is supplied to the gate of PMOS transistor MP0 having its source connected to Vcc, while input signal B is supplied to the gate of NMOS transistor MN0 having its source connected to Vss. The drain of transistor MP0 and the drain of transistor MN0 are commonly connected to line 152, and they are further connected through line 154 (which is connected to line 152) to gate 110 of transistor 100.
Source region 130 is connected through contact 134 to metallic line 132 for other connection(s), while drain region 140 is connected through contact 144 to metallic line 142 for other connection(s).
If the two input signals A and B are supplied to gate 110 of the MOS transistor, the two input signals are transformed into an output signal A' of transistor MP0 and an output signal B' of transistor MN0, and then, these signals are further combined into a signal C, which is supplied through metallic line 120 to gate 110 of MOS transistor 100. Reference numeral 122 indicates a contact between gate 110 and metallic line 120.
Accordingly, signal A' and signal B' pass through the same resistance and capacitance before being supplied to the total gate region.
Referring to FIG. 1, if signals A and B are high level, NMOS transistor MN0 is turned on, thus the potential of gate 110 is lowered to ground potential, Vss. Signals A and B are transformed into signals A' and B' and signal C (combined A' and B') is supplied to gate 110 through parallel lines 110A, and thus the resistance is reduced, and a short time delay occurs.
Meanwhile, if input signals A and B drop to a low potential, PMOS transistor MP0 is turned on, and thus the potential of gate 110 is elevated to Vcc. Signals A and B are transformed into signals A' and B', and signal C is supplied through parallel lines to gate 110, and thus a short time delay occurs.
That is, the signal pass way is the same for making the potential of gate 110 high or low, and the resistance and capacitance remain constant.
FIG. 2 illustrates the layout of MOS transistor 200 in which the length of the gate is extended in order to decrease the current capacity. Source 230 and drain 240 are formed at the opposite ends of gate 210, and again the source/drain regions may be referenced with different names depending on the type of the substrate and the direction of current.
Input signal A is supplied to the gate of PMOS transistor MP0 having its source connected to Vcc, while input signal B is supplied to the gate of NMOS transistor NM0 having its source connected to Vss. The drain of transistor MP0 and the drain of transistor MN0 are commonly connected to line 252, and are further connected through line 254 (which is connected to line 252) to gate 210 of MOS transistor 200.
Source region 230 is connected through contact 234 to metallic line 232 to the outside, while drain region 240 is connected through contact 244 to metallic line 242 to the outside.
When the two signals A and B are supplied to gate 210 of MOS transistor 200, the two signals respectively become output signal A' of transistor MP0 and output signal B' of transistor MN0. Further, the two signals are combined into signal C, which is supplied through metallic line 220 to gate 210 of the MOS transistor. Reference numeral 222 indicates a contact between the gate 210 and metallic line 220.
Accordingly, signals A' and B' pass through the same resistance and capacitance pass way before being supplied to the whole region of the gate.
Referring to FIG. 2, if signals A and B are a high potential, the NMOS transistor MN0 is turned on, with the result that gate 210 is lowered to ground potential, Vss. Signals A and B are transformed into signals A' and B' and combined into signal C, which is supplied through parallel lines to gate 210, and a short time delay occurs.
Meanwhile, if input signals A and B drop to a low potential, PMOS transistor MP0 is turned on and NMOS transistor MN0 is turned off, with the result that gate 210 is elevated to a high potential, Vcc. Since signals A and B become signals A' and B' which are combined into signal C, which is supplied through parallel lines to gate 210, a short time delay occurs. That is, regardless of whether the potential of the gate is elevated or lowered, the resistance and capacitance of the signal pass way remain unchanged.
In the above described conventional technique, both when the potentials of gates 110 and 210 are elevated and lowered, the resistance and capacitance of the signal path remain unchanged. A signal to turn on the MOS transistor and a signal to turn off the MOS transistor are passed through the same path. Therefore, in the case where a marked difference is required between the gate potential elevating time and the gate potential lowering time, a separate resistor has to be installed on the signal path, thereby requiring a larger area.